SPIMode

Syntax:

    SPIMode ( Mode [, SPIClockMode])

Command Availability:

Available on microcontrollers with Synchronous Serial Port (SSP) module.

Explanation:

Mode sets the mode of the SPI module within the microcontroller. These are the possible SPI Modes:

Mode Name Description

MasterSlow

Master mode, SPI clock is 1/64 of the frequency of the microcontroller.

Master

Master mode, SPI clock is 1/16 of the frequency of the microcontroller.

MasterFast

Master mode, SPI clock is 1/4 of the frequency of the microcontroller.

Slave

Slave mode

SlaveSS

Slave mode, with the Slave Select pin enabled.

SPIClockMode is an optional parameter to set the mode of the SPI clock mode. This optional parameter sets both the clock polarity and clock edge.

SPIClockMode Description

0

SPI_CPOL = 0 & SPI_CPHA = 0

1

SPI_CPOL = 0 & SPI_CPHA = 1

2

SPI_CPOL = 1 & SPI_CPHA = 0

3

SPI_CPOL = 1 & SPI_CPHA = 1

You can alternatively use constants to set the SPIClockMode as follows:

    SPIMode ( MasterFast, SPI_CPOL_n + SPI_CPHA_n )

Where the following parameters can be used as a calculation to set the SPIClockMode.

Mode Name Description

SPI_CPOL_0

CPOL = 0

SPI_CPOL_1

CPOL = 1

SPI_CPHA_0

CPHA = 0

SPI_CPHA_1

CPHA = 1

Summary:

When using SPI setting the clock frequency is completed using SPIMode, and the master must also configure the clock polarity and phase with respect to the data. Using the two options as CPOL and CPHA.

The timing diagram is shown below. The timing is further described and applies to both the master and the slave device.

When CPOL=0 the base value of the clock is zero, i.e. the active state is 1 and idle state is 0.

  • For CPHA=0, data are captured on the clock’s rising edge (low→high transition) and data is output on a falling edge (high→low clock transition).
  • For CPHA=1, data are captured on the clock’s falling edge and data is output on a rising edge.

When CPOL=1 the base value of the clock is one (inversion of CPOL=0), i.e. the active state is 0 and idle state is 1.

  • For CPHA=0, data are captured on clock’s falling edge and data is output on a rising edge.
  • For CPHA=1, data are captured on clock’s rising edge and data is output on a falling edge.

When CPHA=0 means sampling on the first clock edge and , while CPHA=1 means sampling on the second clock edge, regardless of whether that clock edge is rising or falling. Note that with CPHA=0, the data must be stable for a half cycle before the first clock cycle.

In other words, CPHA=0 means transmitting data on the active to idle state and CPHA=1 means that data is transmitted on the idle to active state edge. Note that if transmission happens on a particular edge, then capturing will happen on the opposite edge(i.e. if transmission happens on falling, then reception happens on rising and vice versa). The MOSI and MISO signals are usually stable (at their reception points) for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle.

This adds more flexibility to the communication channel between the master and slave.

[graphic

See also SPITransfer